1. Field of the Invention
The invention relates to memory testing and more particularly to a built-in memory test circuit having a dynamic current source.
2. Description of the Related Art
Conventional memory testing checks only if any errors have occurred in basic memory operations, referred to as a functional test. In a functional test, normal operating voltage or current is applied respectively to voltage-based memories such as SRAM, DRAM and FLASH and current-based memories such as magneto-resistive random access memories (MRAM). Stress testing, however, is performed under abnormal conditions such as abnormal temperature or abnormal operating voltage and current respectively for voltage and current-based memories. Memory reliability can thus be further improved. Although stress test costs extra testing time, it is indispensable.
FIG. 1 is a block diagram of a conventional memory current test circuit, illustrating how stress test is performed on a current-based memory. As shown, a memory current test circuit 10 comprises a chip 100 on which are disposed a memory 102 to be tested, a built-in self-test (BIST) circuit 104, and a current mirror 106. The chip 100 is connected externally to automatic test equipment (ATE) 108 having a reference current source 110.
The BIST 104 receives a test signal STEST representing a test algorithm such as March C-test algorithm from the ATE 108. The test algorithm is a sequence consisting of at least one test element, each representing at least one successive memory operation. After receiving the test signal STEST, the BIST 104 generates an operating signal Sop, directing the memory 102 to perform a series of test operations represented by the test algorithm. During a memory test, the BIST 104 further receives a data signal SQ, checking for errors in the data signal SQ, and returning an error output signal SERRO to the ATE 108 if any are detected.
The current mirror 106 is connected to the reference current source 110 within the ATE 108 to receive a reference current IREF provided by the reference current source 110, generating a test current ITEST required in the memory testing according to the reference current IREF, and then providing the test current ITEST to the memory 102.
To perform a stress test on the memory 102, it is required to provide the memory 102 with a different test current ITEST. The reference current source 110 of the ATE 108 thus must be able to provide a different reference current IREF For this reason, the reference current source 110 is designed to be switched via a control of ATE 108 to provide the different reference current IREF. Alternatively, the current mirror 106 must be able to receive required amount of the reference current IREF. However, extra pins are required in the reference current source 110 or the current mirror 106 to select an appropriate reference current IREF such that the required ITEST is generated.
Further, ATE 108 is required to reset ITEST to different values in a stress testing. Much time is thus wasted. To conserve test time, all writing operations are generally performed with the same test current ITEST in a March C- test algorithm. More specifically, writing operations performed with different test currents are included in neither the same test element nor the different test elements in a March C- test algorithm. For the same reason, functional testing and stress testing are performed with a different test current ITEST but the same test algorithm.
For example, a Mach C- test algorithm for a functional testing is:{(w10);(r0, w11);(r1, w10);(r0, w11);(r1, w10);(r0)}  (1),which comprises six test elements, where w and r in any test element respectively represent writing and reading operations; 0 and 1 behind w or r respectively represent bit to be read or written; ,  and  represent the operating direction of memory address, respectively denoting upwards, downwards, arbitrarily selected from upwards and downwards; suffix “1” behind each of the writing operations within { } represent that all the writing operations are performed with a first test current. The Mach C- test algorithm includes a total of ten operations performed with the same test current. This March C- test algorithm is often called a 10N test algorithm where N denotes the capacity of the memory. Also, 10N is representative of the test time.
Stress test, however, is generally performed by repeating the same test algorithm with different test currents. More specifically, the test algorithm in a stress test is, the test algorithm (1) followed by another test algorithm:{(w20);(r0, w21);(r1, w20);(r0, w21);(r1, w20);(r0)}  (2)where suffix “2” behind each of the writing operations within { } represent that all the writing operations are performed with a second test current. The test algorithm (2) costs 10N of test time. Before a test represented by the test algorithm (2) is performed, the ATE 108 must reset the test current ITEST. Resultantly, the total test time is 20N+TATE, where TATEis setting time of the test current ITEST consumed by the ATE 108. Similarly, when the test current ITEST is to be changed subsequently to perform further another similar test, the total test time is increased by (10N+TATE), and so forth. Consequently, the total test time in a stress test is very long.
In respect to other prior technologies, Jian Liu et al propose a built-in current sensor to control operating current in memories to enhance efficiency of memory testing (referred to “SRAM test using on-chip dynamic power supply current sensor” in Proc. IEEE Int. Workshop on Memory Technology, Designing and Testing (MTDT), Aug. 1998, pp. 57-63.). Hong-Sik Km et al. in Korea also disclose a paper on memory testing using two reference currents by comparing the operating current of the memory and the two reference currents to detect errors in the memory (referred to (“DPSC SRAM transparent test algorithm”, in Asian Test Symposium (ATS), Nov. 2002 Page(s):145-150)). However, extra pins are needed to select an appropriate test current. Both of the two conventional technologies focus merely on partial test components or test current in a normal test, not with a complete environment.
In the conventional technology, when a test is to be performed on different memories on a system on a chip (SOC), ATE is required to reset the test current for the memories individually since different memories require different test currents. This means that different memories can only be tested by turn and not in parallel at the same time. Consequently, if N memories are to be tested, the total test time is:
                                                        ∑              2              N                        ⁢                                          T                ATE                            ⁡                              (                n                )                                              +                                    ∑              1              N                        ⁢                                          T                M                            ⁡                              (                n                )                                                    ,                            (        3        )            where TATE(n) denotes the setting time of the test current for the nth memory consumed by the ATE, and TATE(n) denotes the test time of the nth memory. The total test is very long.